1. Field of the Invention
Embodiments of the present invention generally relate to the fabrication of integrated circuits. More particularly, embodiments of the present invention relate to methods for depositing carbon-doped silicon nitride layers that have compressive stress.
2. Description of the Related Art
Integrated circuits are composed of many, e.g., millions, of devices such as transistors, capacitors, and resistors. The transistors may include metal-oxide-semiconductor field effect transistors (MOSFETs).
A MOSFET includes a gate structure that is disposed between a source region and a drain region defined in a semiconductor substrate. The gate structure or stack generally comprises a gate electrode formed on a gate dielectric material. The gate electrode controls a flow of charge carriers beneath the gate dielectric in a channel region that is formed between the drain region and the source region so as to turn the transistor on or off.
The performance of a MOSFET device can be improved by several methods, such as reducing the supply voltage, reducing the gate dielectric thickness, or reducing the channel length. However, such methods are becoming more difficult as devices become smaller and more densely spaced on semiconductor substrates. For example, if a very thin gate dielectric is used, dopants from the gate electrode may penetrate through the gate dielectric into the underlying silicon substrate. A very thin gate dielectric may also increase gate leakage that increases the amount of power consumed by the gate and eventually damages the transistor.
Straining the atomic lattice of materials in devices is a recently developed, alternative method of improving device performance. Straining the atomic lattice improves device performance by increasing carrier mobility in a semiconductor material. The atomic lattice of one layer of a device can be strained by depositing a stressed film over the layer. For example, stressed silicon nitride layers used as etch stop layers over a gate electrode can be deposited to induce strain in the channel region of the transistor. The stressed silicon nitride layers can have compressive stress or tensile stress. The selection of a compressive or tensile stress layer is based on the type of underlying device. Typically, tensile stress layers are deposited over NMOS devices, and compressive stress layers are deposited over PMOS devices. It has been observed that PMOS device performance increases approximately linearly with the level of compressive stress of a silicon nitride contact liner or etch stop over the device.
While plasma-enhanced chemical vapor deposited (PECVD) silicon nitride (SiN) layers that have high compressive stress levels have been developed, there remains a need for layers with higher levels of compressive stress to further improve device performance.